Community Newsletter: February 2014

IN THIS ISSUE:

Message from the Chair
Shishpal Rawat reveals what you’ll experience at this year’s DVCon
Accellera Day at DVCon 2014
Join us at this day-long event dedicated to technical standards
Working Group Spotlight: Multi-Language
The MLWG hosts Birds of Feather at DVCon
Setting the Standard Blog
DVCon Plants a New Seed in Europe
Upcoming Events
ESCUG Meeting at DATE, DVCon Europe

On the Road to DVCon 2014

Shishpal Rawat, Accellera Systems Initiative Chair DVCon (Design and Verification Conference and Exhibition) is right around the corner! The conference focus is on the front end, design and verification of electronic systems and integrated circuits with technical and practical information for users that they can immediately implement in their jobs. There are many exciting things to look forward to at this year’s conference including Accellera Day on Monday featuring in-depth tutorials on UVM, UPF, OCP, SystemC and SystemC AMS. Lunch features the presentation of Accellera's technical excellence award, followed by an industry panel on the future of mixed-signal verification. New this year is a booth crawl in the evening through the DVCon Expo. With cocktails and appetizers hosted by our exhibitors, this is the place to connect with colleagues in a casual and friendly environment.

On Tuesday, Cadence CEO Lip-Bu Tan will give the keynote on "An Executive View of Trends and Technologies in Electronics" to reveal the new design technologies that are essential to continuing innovation. Paper sessions during the conference will offer in-depth discussions on topics such as higher level, low power and analog/mixed-signal design, as will poster sessions and expanded tutorials. Featured events include JL Gray’s Industry Leaders Panel titled, "Did We Create the Verification Gap?" which will examine the characteristics of a typical verification effort and how to bridge the gap from concept to implementation.

Accellera's Multi-Language Working Group (MLWG) will host a Birds of Feather session on Monday evening. I invite you to join us in this open forum as we discuss a new standard for multi-language verification and how you can contribute.

With 12 technical sessions, a conference record 12 tutorials, a poster session with a record 30 posters, and a record number of exhibitors, 12 of them first-timers, DVCon 2014 is bound to be the most exciting conference in our history! I would like to extend my personal invitation to join us and be a part of this vibrant and insightful design and verification community.

Sincerely,

Shishpal Rawat, Accellera Systems Initiative Chair
February 2014

P.S. DVCon is hosting a Fall conference in Europe! Read about it here.

Accellera Day at DVCon

Monday, March 3, 2014
8:30am - 7:00pm
DoubleTree Hotel, San Jose CA

Accellera invites you to a special day dedicated to technical standards at the 2014 Design and Verification Conference. Connect with experts and users as we learn, share, and network on the latest in EDA and IP standards innovations.

View full details >

Sponsors:
Accellera Global Platinum: ARM, Cadence, Mentor Graphics, Synopsys
Accellera Platinum: Jasper

Working Group Spotlight:

Multi-language Working Group (MLWG) Birds-of-a-Feather

Monday, March 3, 2014
5:30pm to 7:30pm
Oak Ballroom
DoubleTree Hotel, San Jose CA

In 2012, the Accellera Board tasked representatives from six electronics companies to define a standard for multi-language verification interoperability. Please join Warren Stapleton, Chair of the Multi-Language Working Group (MLWG), as he introduces the group, reviews its charter, and explains the progress of the group in an open forum. This will be followed by a more detailed working session for anyone interested. Join us to learn more about this exciting topic.

The audience for this session is IP stakeholders — the authors, users, and EDA tool vendors active, or wanting to become active, in the standardization of languages or methodologies based on or using SystemVerilog, UVM, and/or SystemC. The intent is to provide enough detail for a high-level overview on the multi-language verification concepts and requirements in the context of standardization.

The agenda for this birds-of-a-feather meeting is as follows:

Introduction to the MLWG (20 min)
- Charter, goals, requirements, current status
Proposed architecture and intended use cases (40 min)
- Discuss a specific use case in more detail to get feedback and ideas
- Touch upon open issues that remain ahead of the MLWG to solve
Break (5 min)
MLWG Working Session (50 min)
- Roadmap including milestones
- LRM structure/content
- Standard development process and how to contribute

DVCon Plants a New Seed in Europe

Setting the Standard Blog

By Adam Sherer, Vice-chair of the Promotions Group, Accellera

Adam Sherer

In the 26 years since the first seed for DVCon was planted, the conference has grown into a vibrant event branching out from RTL design and verification to IP standards, systems design, and systems verification. This spring, Accellera is proud to announce that a new seed is being planted in Europe.

The call for abstracts is now open for DVCon Europe. The event will be held October 14 - 15, 2014 in Munich, Germany. Similar to DVCon, the new event will include tutorials, paper sessions, and a vendor exhibition, with many more details available on the website: www.dvcon-europe.org. Whether you submit an abstract or simply attend, the new event will be nurtured with your knowledge and it will grow strong.

Upcoming Events

European SystemC Users Group Meeting (ESCUG 29)

SystemC

March 25
Dresden, Germany
Co-located with DATE 2014

Call for Contributions is open through February 28!
View full details >

DVCon Europe

October 14-15
Munich, Germany
www.dvcon-europe.org

Call for Abstracts is Open!
Be one of the first presenters at this new conference in Europe!
Find out more >

DVCon has expanded to Europe to bring chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.

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