Join Us for Accellera Day at DVCon U.S. 2016
Monday, February 29
9:00am-5:00pm
Design & Verification Conference and Exhibition
DoubleTree Hotel, San Jose, CA
Accellera invites you to join us as we open DVCon U.S. with a day filled with insights into technologies that you can apply immediately and those that will help to define the future.
Agenda
9:00am-12:00pm
- Tutorial 1: Preparing for IEEE UVM Plus UVM Tips and Tricks
- Tutorial 2: SVA Advanced Topics: SVAUnit and Assertions for Formal
12:00pm-1:30pm — Accellera Luncheon
2:00pm-5:00pm
- Tutorial 3: Cut Your Design Time in Half with Higher Abstraction
- Tutorial 4: SystemVerilog-AMS: The Future of Analog/Mixed Signal Modeling
5:00pm -7:00pm — DVCon Expo and Booth Crawl
Tutorial 1: Preparing for IEEE UVM Plus UVM Tips and Tricks
UVM is poised to make the great leap to the IEEE with the work in the 1800.2 committee. In preparation for this new step and as part of the work done in the iEEE, there are changes you should know about the IEEE version of the standard. Some of the most significant changes are involve retiring hidden APIs. Knowing what these are can help you prepare for the new standard. This part of the tutorial will provide code examples and recommendations from experts working in the IEEE.
While we are preparing for the future, we do need to get chips out now. Debugging UVM testbenches can be extremely difficult because errors often appear in lines of SystemVerilog code that make up the UVM package, as opposed to the user written code. There are also a number of common errors, that are hard to recognize because the compiler gets off on the wrong track early, and never recovers. Most of these errors can easily be eliminated by following a structured approach to debugging that targets these common errors first. This part of the tutorial will walk through an introduction of UVM testbench features, a working examples including common errors and fixes, and conclude with the built in debugging features in UVM and how to use them./p>
Organizer:
Adam Sherer - Accellera Systems Initiative
Speakers:
Doug Perry- Doulos
Srinivasan Venkataramanan - CVC Pvt., Ltd.
Srivatsa Vasudevan - Synopsys, Inc.
Tutorial 2: SVA Advanced Topics: SVAUnit and Assertions for Formal
SystemVerilog Assertions (SVA) is one of the central pieces in functional verification for protocol checking or validation of specific functions. This tutorial will introduce advanced topics for assertion based verification including SVAunit and SVA for formal. This first half of the tutorial discusses SVA planning, coding guidelines, SVAUnit (SVAUnit framework, self-checking tests, debug), and test patterns. Planning includes parametrization, temporal sequence composition, sequence reuse and also consider how the SVA package will be integrated with other verification methods. Coding guidelines ensure efficiency as well as avoid common implementation pitfalls.
SVAUnit is a new concept that specifically addresses these requirements and more:
- decouple assertion validation code from assertion definition code
- simplify the generation of a wide range of stimuli, from 1 bit signal toggling to transactions
- provide the ability to reuse scenarios
- provide self-checking mechanisms
- report test status automatically
- integrate with major simulators
This half of the tutorial closes with the presentation of SVA test patterns for the most common temporal sequences and scenarios. In the second half of the tutorial we learn how to define objects in SystemVerilog by specifying their properties formally. Then, this formal specification is used for assertion or coverage purposes with real USB interface examples and show the advantages over scripting and SystemVerilog always blocks. For example, the Perl scripting was at least 3X less efficient, while using SystemVerilog with always structures was 6X worse. In addition, a well-defined SVA library is part of the verification methodology where generic sequences are reused.
Finally, the inclusion of SVA reduces the debug effort since SVA points to a specific area where the error was detected. This second half of the tutorial contains 3 sections, the first part explains the formal specification where its basics are clearly described using SystemVerilog language as a vehicle. The second and third part cover the formal specification applications on assertions and coverage respectively.
Organizer:
Adam Sherer - Accellera Systems Initiative
Speakers:
Ionut Ciocirlan - AMIQ srl
Andra Radu - AMIQ srl
Rodrigo Calderon-Rico - Intel Corp.
Israel Tapia - Intel Corp.
Accellera Luncheon
Accellera Systems Initiative invites all attendees of the Monday tutorials to the Accellera-sponsored luncheon.
Shishpal Rawat, Accellera Chair, will provide an Accellera update, and the Annual Technical Excellence Award will be presented. In addition, members of the Portable Stimulus Working Group will provide an update on WG activities.
Organizer:
Adam Sherer - Accellera Systems Initiative
Speakers:
Tom Fitzpatrick - Mentor Graphics Corp.
Shishpal Rawat - Intel Corp.
Tutorial 3: Cut Your Design Time in Half with Higher Abstraction
In the quarter century that RTL has been our main digital design abstraction, the silicon devices that we build have grown 4 orders of magnitude in gate count. Our projects are managing millions of lines of code eating into our design and verification efficiency. Such dizzying growth makes the design engineer wonder — is it time to move up abstraction again?
We in the Accellera SystemC Synthesis Working Group (SSWG) think the answer is YES. The most recent draft of a synthesizable subset standard for SystemC has been available for public review and we’d like to introduce it to you. This tutorial is focused on the engineer today who is coding in Verilog/SystemVerilog or VHDL. We will explain how to use the language subset to write synthesizable models at a higher level of abstraction than RTL. We will provide real code examples comparing algorithms written at RTL and those written using the synthesizable subset, explaining the reasons behind the coding choices and the downstream implications for RTL and gates. We will also discuss how a synthesis standard is the foundation for a full design and verification ecosystem at a higher level of abstraction and the value that can bring to the designer.
We’ll conclude with some potential directions for the synthesis subset that will further enable the HLS ecosystem and a Q/A panel session with our presenters.
Organizer:
Adam Sherer - Accellera Systems Initiative
Speakers:
Bob Condon - Intel Corp.
Frederic Doucet - Qualcomm, Inc.
Peter Frey - Mentor Graphics Corp.
Mike Meredith - Cadence Design Systems, Inc.
Dirk Seynhaeve - Intel Corp.
Tutorial 4: SystemVerilog-AMS: The Future of Analog/Mixed-Signal Modeling
In the 2012 revision of SystemVerilog, nettypes and interconnect were added to provide language features for modeling analog/mixed-signal (AMS) circuits. While these constructs are useful, they do not provide a complete solution for those interested in complex AMS modeling scenarios. Verilog-AMS is a much more complete AMS modeling solution, but it is based on the Verilog 2005 standard which has been superseded by SystemVerilog.
Over the past two years, a small group of Verilog-AMS and SystemVerilog experts have been meeting with the goal of unifying SystemVerilog and Verilog-AMS. This tutorial will provide an introduction to the concepts underlying the upcoming SystemVerilog-AMS language standard.
Organizer:
Scott Little - Intel Corp.
Speakers:
Martin Vlach - Mentor Graphics Corp.
Scott Little - Intel Corp.
DVCon Expo Booth Crawl
DVCon is doing it again!
You won't want to miss the annual DVCon Booth Crawl on the exhibit floor. Cocktails and conversations in a casual environment with the DVCon exhibitors.
By attending the Booth Crawl you'll be automatically entered into a drawing for a $500 VISA gift card. The winner must be present to win and will be announced Monday night.
Mingle from booth to booth while enjoying food and drinks provided by participating exhibitors.
2016 Global Sponsors
