Join Us for Accellera Day at DVCon 2014

Accellera Day
2014 Design and Verification Conference
Monday, March 3
8:30am - 7:00pm
DoubleTree Hotel, San Jose, CA

Accellera Systems Initiative invites you to a special day dedicated to technical standards at the 2014 Design and Verification Conference. Find out the latest in EDA and IP standards being developed and implemented by today’s leading electronics companies. Accellera Day features in-depth tutorials on UVM, UPF, OCP, SystemC and SystemC AMS. Our sponsored luncheon features a discussion of the future of mixed-signal verification as well as presentation of the annual Technical Excellence Award for outstanding achievement and contribution to Accellera standards.

Join us at this day-long event to connect with experts and users as we learn, share, and network on the latest in standards innovations.

Agenda

9:00am - 12:00pm		Tutorial 1: UVM — What’s Now and What’s Next Read abstract
9:00am - 12:00pm		Tutorial 2: Using UPF for Low Power Design and Verification Read abstract
12:00pm - 1:15pm		Sponsored Lunch and Technical Excellence Award Presentation View details
2:00pm - 5:00pm		Tutorial 3: Case Studies in SystemC Read abstract
2:00pm - 5:30pm		Tutorial 4: Experience the Next ~Wave~ of Analog and Digital Signal Processing Using SystemC AMS 2.0 Read abstract
2:00pm - 5:00pm		Tutorial 5: OCP: The Journey Continues Read abstract
5:00pm to 7:00pm		DVCon Expo Booth Crawl Find out more

TUTORIAL 1: UVM — What’s Now and What’s Next

UVM The Universal Verification Methodology (UVM) has experienced great adoption and growth throughout the industry since its initial release as an Accellera standard 3 years ago. Verification engineers, EDA suppliers, service providers, and others throughout the electronics industry are actively creating verification environments following the UVM principles. Concepts like stimulus generation based on sequences, test execution using phases, communication based on transaction-level modeling (TLM), and the introduction of a register layer, all have significantly contributed to the maturity of functional verification practices.

The presenters will share their experiences on both pragmatic topics that can be applied on UVM 1.1 and advanced topics for the next update of the standard. This tutorial will assume SystemVerilog language knowledge when discussing technical content and presenting detailed examples. Among the topics will be sequence creation, register layer use (both beginner and advanced), TLM-based communication, test execution using run-time phases, and messaging enhancements. All verification engineers – from those just starting to work with the UVM to those with years of experience – will gain new knowledge from the tutorials.

Organizer:
Thomas Alsop - Intel Corp.

Speakers:
Thomas Alsop - Intel Corp.
John Aynsley - Doulos
Shawn Honess - Synopsys, Inc.
Tom Fitzpatrick - Mentor Graphics Corp.
Uwe Simm - Cadence Design Systems, Inc.

TUTORIAL 2: Using UPF for Low Power Design and Verification

UPF This tutorial presents the latest information on the Unified Power Format (UPF), based on IEEE Std 1801-2013 UPF which was released in late May of last year. Beginning with a review of the concepts, terminology, commands, and options provided by UPF, it will cover the full spectrum of UPF capabilities and methodology, from basic flows through advanced applications, with particular focus on incremental adoption of UPF. Tutorial attendees will come away with a thorough understanding of UPF usage in low power design and verification flows and its role in energy aware system design.

Organizers:
Erich Marschner - Mentor Graphics Corp.
John Biggs - ARM Ltd.

Speakers:
Erich Marschner - Mentor Graphics Corp.
John Biggs - ARM Ltd.
Sushma Honnavara-Prasad - Broadcom Corp.
David Cheng - Cadence Design Systems, Inc.
Jon Worthington - Synopsys, Inc.
Nagu Dhanwada - IBM Corp.

TUTORIAL 3: Case Studies in SystemC

SystemC For more than a decade, SystemC has been used by system architects and design engineers. In more recent times Transaction Level Modeling (TLM2) and virtual prototyping have been an integral part of rewriting some of the models and enhancing the design and verification methodologies from earlier efforts. They have continued to deploy evolving methodologies in new application areas such as radio base station and network processors to bring-up software months ahead of the traditional approach. Other users have attempted to bridge the interoperability gap between SystemC and Universal Verification Methodology (UVM) based on SystemVerilog and other HDLs. In this tutorial, hands-on users and tool developers share their recent experience and describe advanced methodologies that have helped them achieve significant benefits.

Organizer:
Yatin Trivedi - Synopsys, Inc.

Speakers:
John Aynsley - Doulos
Henrik Svensson - Ericsson
Christian Sauer - Cadence Design Systems, Inc.
Martin Barnasconi - NXP Semiconductors
Donald Cramb - Synopsys, Inc.
John Stickley - Mentor Graphics Corp.

TUTORIAL 4: Experience the Next ~Wave~ of Analog and Digital Signal Processing Using SystemC AMS 2.0

SystemC Today’s embedded systems and SoCs contain more and more physical interface IPs (e.g. USB, PCIe, DDR, SATA and HDMI) and mixed-signal IP (e.g. Sigma-delta-ADCs, DACs and PLLs) which directly interact with the digital HW/SW subsystems. For example, many of these mixed-signal IP’s are registered-controlled and can be configured and calibrated via the on-chip processor.

Furthermore, while data-rates continue to increase, design of these high-speed peripherals requires inclusion of the analog/mixed-signal behavior in the overall signal processing chain to guarantee error-free transmission and reception over the physical channels. This requires new means to model and simulate the algorithms and signal processing capabilities of these peripherals, in combination with the HW/SW subsystems at functional and architecture level. Especially for this purpose, the SystemC language standard has been extended with powerful mixed-signal and signal processing modeling features to tackle the challenges in heterogeneous electronic system-level design and verification.

This tutorial will be conducted as a true “hands-on” session: after a basic introduction on the SystemC AMS 2.0 modeling concepts and methodology, everyone is encouraged to actually create models, run simulations and look at waveforms! To facilitate this, information distribution will be made available for the attendees, including a fully prepared system-level modeling environment, which they can run immediately on their own laptop.

In an interactive way, presentations and “labs” will be alternated introducing both analog and digital signal processing exercises, giving the attendees a valuable introduction of the existing and new features of SystemC AMS. Examples are the creation of analog filters, analog-to-digital converters and completion of a transceiver system using digitally modulated signals.

This highly technical tutorial targets system engineers, integrators, architects and verification engineers active in industrial projects where analog and digital signal processing functionality comes together and where interoperability between mixed-signal and HW/SW subsystems becomes apparent. Note that the tutorial does not target analog/mixed-signal circuit-level and mixed transistor/RTL modeling; instead, it will focus on abstract mixed-signal modeling for system-level design and verification. Therefore experience with algorithm and C/C++/SystemC languages is highly preferred.

So in case you are interested to experience the next ~wave~ of analog and digital signal processing using SystemC AMS? Join us at DVCon 2014!

Speakers and trainers in this workshop are recognized leaders in the field of mixed-signal system-level modeling:

Karsten Einwich, Fraunhofer IIS/EAS Dresden, Germany - Creator of the SystemC AMS compliant proof-of-concept implementation
François Pêcheux, University Pierre et Marie Curie, Paris, France - Leader in scientific innovation using SystemC AMS for RF, communication and biomedical applications
Martin Barnasconi, NXP Semiconductors, Eindhoven, The Netherlands - Driving SystemC AMS standardization in the Accellera Systems Initiative from an industrial perspective and chair of the SystemC AMS Working Group.

Similar sessions have been organized in Europe at major conferences and events. The organizer and speakers would like to bring the success of SystemC AMS in Europe to other regions of the world.

Installation instructions (prior to the event)

To conduct the exercises with SystemC-AMS in the practical sessions (the “labs”), registered participants will receive the software installation instructions one week prior of the event by e-mail. The minimum requirements for the installation of the system-level modeling environment are:

Windows version Windows 2000, Windows XP, Windows 7, Windows 8 (not Vista)
Minimal RAM: 2GB
Minimal free disk space: 4GB

In case of installation questions or problems, registered participants can contact the organizers via email by This email address is being protected from spambots. You need JavaScript enabled to view it..

Organizer:
Martin Barnasconi - NXP Semiconductors

Speakers:
Karsten Einwich - Fraunhofer IIS
François Pêcheux - Univ. Pierre et Marie Curie
Martin Barnasconi - NXP Semiconductors
Torsten Mähne - Univ. Pierre et Marie Curie

Tutorial 5: OCP: The Journey Continues

This tutorial will present the past, present and future of the Open Core Protocol IP interface socket standard, which was transferred to Accellera in October, 2013. The tutorial will provide some history and a basic introduction to the OCP Specification itself, and then discuss a variety of topics crucial to the use of OCP in SoC designs: verification IP support, TLM 2.0 SystemC support and IP-XACT support. The tutorial will close with a discussion of future needs in IP core interfacing, and where future version of the OCP standard may play a role.

Organizer:
Drew Wingard - Sonics, Inc.

DVCon Expo Booth Crawl

NEW THIS YEAR!!

You won’t want to miss the inaugural DVCon Booth Crawl on the exhibit floor. Cocktails and conversations in a casual environment with the DVCon exhibitors. Mingle from booth to booth while enjoying food and drinks provided by the exhibitors.

By attending the Booth Crawl you’ll be automatically entered into a drawing for a $500 VISA gift card. The winner must be present to win and will be announced Monday night.